Heterogeneous Multi-core Architectures

Asymmetry-Aware Scheduling in Heterogeneous Multi-core Architectures

As threads of execution in a multi-programmed computing environment have different characteristics and hardware resource requirements, heterogeneous multi-core processors can achieve higher performance as well as power efficiency than homogeneous multi-core processors. To fully tap into that potential, OS schedulers need to be heterogeneity-aware, so they can match threads to cores according to...

A Reconfigurable Processor for Heterogeneous Multi-Core Architectures

Performance of applications with computationally intensive kernels can be improved by a general-purpose processor used together with application-specific hardware accelerators. To accelerate a wide range of applications with different kernels, a runtime reconfigurable fabric (such as an embedded FPGA) is used. Each application can deploy its own accelerators onto the fabric in order to improve ...

Dynamically Reconfigurable NoC for Future Heterogeneous Multi-Core Architectures

Traditional bus based communication medium will prove to be a bottleneck in achieving the high processing requirements in future SoC, especially with the on-chip communication requirements rising over 9 GB/s. NoC is considered as a solution to this communication bottleneck. The NoC architecture is generated by choosing a network topology, one of the routing and switching schemes and fixing a pa...

Ompss: a Proposal for Programming Heterogeneous Multi-Core Architectures

A Unified Runtime System for Heterogeneous Multi-core Architectures

Approaching the theoretical performance of heterogeneous multicore architectures, equipped with specialized accelerators, is a challenging issue. Unlike regular CPUs that can transparently access the whole global memory address range, accelerators usually embed local memory on which they perform all their computations using a specific instruction set. While many research efforts have been devot...